Glitch Power Reduction for Low Power IC Design

Because of the rapid growth of portable electronics, high density integrated circuits with low energy consumption and low electromagnetic interference (EMI) at high speeds are needed. It is well known that dynamic power dissipation is directly related to the number of the signal transitions in the circuit. Functional signal transitions are desirable, where spurious transitions (or glitches), caused by unequal propagation delays of input signals to the gate, are not desirable. Glitches multiply as they propagate through a combinational logic block and could occupy 20 to 70 percent of signal transitions [1]. In Boolean design, gate sizing and gate registration are used to reduce glitches. However, these techniques are delay sensitive and cannot truly eliminate glitches due to unequal propagation delays of input signals resulting from layout parasitics in deep submicron CMOS technology. In this paper, we propose the use of the NULL Convention Logic (NCL) threshold gates and NCL design paradigms to eliminate spurious signal transitions. A 4 bit by 4bit multiplier is designed for the evaluation of glitch power and signal bounce from supply voltage variation. The effect of voltage scaling on the clockless circuit is also evaluated.